1. Field of the Invention
An object of the present invention is a memory as well as a method by which an electronic integrated circuit prototype including a memory of this type is designed or defined. It can be applied in memories where the memory cells have a memorizing element which is an electrically programmable (EPROM or EEPROM) floating gate transistor. It concerns memories capable of containing both random-access memory cells and read-only memory cells. Random-access memory cells are memory cells that can be programmed by a microprocessor which manages the memory according to needs expressed by a user. Read-only memory cells are not designed to be programmed by this microprocessor. They have information relating to operating instructions for the integrated circuit, the microprocessor or the memory itself. They may also contain secret codes, access keys or protecting algorithms.
2. Description of the Prior Art
One of the main problems presented by read-only memory cells lies in the decipherable nature of the information that they contain. Indeed, and this is even truer when the read-only memory cells are made in juxtaposed memory areas, using a different technology from that of memory areas with random-access memory cells, the information content of the read only memory cells can be revealed by means of a microscope. For example, in a simple technology, the content of the information programmed can be revealed by the presence or absence of a connection, the presence or absence of a fuse or the presence or absence of an electronic junction or diode. In the case of fuses, the read-only memory cells may be defined directly -by, the user, by programming. In other instances, the areas of a read-only memory should be defined at early stage in the process for manufacturing the electronic integrated circuit which contains it. However, in all cases, the presence or absence of these electronic functions makes the deciphering of the content of the read-only memory cells of the read-only memory relatively easy.
A fraudulent person who might attempt to analyze an integrated circuit of this type aimed at unveiling the content of these read-only memories, will also find his work facilitated by the fact that the technology used to manufacture the read-only memory cells is also very different from the technology for manufacturing memory cells of the random-access memory. For manufacturing reasons, and as if the aim were to make fraud more simple, the memory areas of random-access memory cells and those of read-only memory cells are geographically well separated in the memory of the circuit. So much so that the fraudulent person has no difficulty whatsover in locating these read-only memory cells. After depassivation of the electronic integrated circuit, after removing the protective layers, he may then easily gain access to the information contained.
Another problem of read-only memory cells is located in the feature wherein their size can be modulated. For although, for certain applications, a read only memory area of relatively small-sized read-only memory cells is warranted, other more demanding applications may call for a bigger memory zone. Electronic circuits manufactured in this way cannot then have any universal character. They have to be divided into categories, differentiated from one another, for example, by the size of the read-only memory areas which they might possess. This diversity of manufacture does not lend itself to high profitability, nor to high manufacturing reliability.
Another problem has been encountered in the designing of electronic integrated circuits which include memory areas: the finalizing stage of the prototype should take into account the intricate functioning of the total integrated circuit. The choices relating to the category of electronic integrated circuits, with a given number of read-only memory cells, then determine the final result. The drawback of these choices is that they have to be made at a stage well before the circuits are manufactured, even well before the prototype is made. This may lead, in the event of error, to a great deal of time being lost in making the electronic integrated circuit in question. Ultimately, these choices should guide the manufacture of the desired electronic circuits from the very outset. They condition the finalizing of the functions and manufacturing possibilities of the circuit in question. This constraint goes against the trend of developments hitherto in this field where, as in the so-called pre-diffused technique, it is sought to perform as many stages as possible for the manufacture of the electronic integrated circuits before defining it for a given application. In short, the goal to be achieved, for a memory area with a given memory size, consists in making the distinction between the portion reserved for random-access memory cells and that reserved for read-only memory cells as late as possible.
An object of the invention is to overcome these drawbacks by proposing a new memory plane where the technology for manufacturing the read-only memory cells is partly the same as that for the manufacture of random-access memory cells. The invention is based on the principle that, in a non-volatile random-access memory cell having a storage element which is a floating gate transistor, a known method employed consists in doping the conduction channel of this floating gate transistor with impurities of the same type as the substrate (enhancing) in order to promote the programming conditions of this cell. For, it is known that if the conduction channel is doped, it is doped only at the surface. When this transistor is put into saturation so that it can be programmed, then, the injection of electrons in the floating gate is all the more efficient. Quite simply, if the channel is not doped, all the channel and the electrons injected from the bottom of the channel partly lose their energy for rising to the surface of this channel, towards the gate oxide which separates them from the floating gate. Since their energy has been reduced, they are then not mobile enough to cross this gate oxide barrier. The injecting efficiency is then lower.
The fact of injecting impurities in a conduction channel in order to promote the programming operation has the effect of shifting the conduction threshold voltage of these floating gate transistors upwards. For example, the drain-source voltage at which a non-programmed floating gate transistor starts conducting is about one volt when its conduction channel is not doped but becomes about 1.5 volts when its conduction channel is doped. The consequence of this is that when the information content stored in a memory cell of this type is being read, and depending on a drain-source voltage imposed on this transistor, the current which it conducts will be smaller when this conduction channel is doped than when it is not doped.
The invention turns this phenomenon to advantage, for example by exaggerating it in order to differentiate between non-programmed read-only memory cells and programmed read-only memory cells. A distinction is then made between the current that a read-only memory cell is capable of putting through depending on whether its conduction channel is more doped or less doped depending on the programming state which is sought to be imposed on it.
This approach gives all the expected advantages. In particular, the rate of impurities implanted in a conduction channel cannot be detected by microscopic examination. Furthermore, the choice of one and the same type of cell, namely cells with floating gate transistors, to make both the read-only memory cells and the random-access memory cells makes it possible, in order to build a prototype, to define a memory which is entirely provided with random-access memory cells, with floating gate transistors, and makes it possible to set the distribution of these cells among random-access memory cells and read-only memory cells after the prototype finalizing stage. For a memory with a given capacity, it then becomes quite possible to substantially increase the size of the read-only memory cells. In all cases, the size of the overall memory area may remain identical.
Furthermore, the operation for implanting the impurities in the conduction channel of the floating gate transistors is one which takes place fairly late in the manufacturing process. Hence, numerous operations may be performed to manufacture a universal electronic integrated circuit before fitting it to specific purposes. Furthermore, the implanting operation is not specific in itself. For, given that implantation is already necessary for the memory area of the random-access cells but that this implantation is not done in the peripheral circuits of the memory area, it is already necessary to use a mask. All the photo-masking operations required by a manufacturing method for memory areas according to the invention then have the sole effect of defining this mask in a different way, possibly in a more precise way, to share out the different types of cells.
Furthermore, in an application where the rate of impurities implanted in the programmed read-only memory cells is exaggerated, another mask may be warranted as the case may be. However, this other mask is made and applied under the same conditions than the preceding one.
An object of the invention therefore, is a memory firstly, provided with electrically programmable random-access memory cells, these cells being of the type that comprise a floating gate transistor, and secondly comprising read-only memory cells, wherein the read-only memory cells are also of the type comprising a floating gate transistor but where the programming state is differentiated by the conduction performance of the conduction channel of the floating gate transistor.
Another object of the invention is a method to define an electronic integrated circuit comprising a memory array provided with random-access memory cells and read-only memory cells, said method comprising the following steps:
a prototype is made containing only random-access memory cells, PA0 the position at which the random-access memory cells are designed to become read-only memory cells in the circuit to be defined, is determined, PA0 and an integrated circuit is made the memory of which is designed in accordance with the above indicated memory array, the read-only memory cells being placed at the defined corresponding positions.